(1) Field of the Invention
The present invention relates to processes used to fabricate semiconductor devices, and more specifically to a process used to create a small diameter opening, in an insulator layer, used to accommodate a dual damascene metal structure.
(2) Description of Prior Art
The use of damascene, or dual damascene metal structures, have allowed the semiconductor industry to reduce process complexity and cost. The ability to fabricate an overlying, wide diameter, metal interconnect structure, and an underlying, narrow diameter, metal via structure, using only a single metal deposition, and patterning procedure, has allowed the cost and process complexity objectives to be realized. A dual damascene opening, formed in a composite insulator layer, comprised of a wide diameter opening, and of an underlying, narrower diameter opening, is used to accommodate the subsequent dual damascene metal structure. However as demands for sub-micron devices increase, the photolithographic limits, in regards to the critical dimension of the narrow diameter opening, of the dual damascene opening, becomes critical.
This invention will teach a process in which a dual damascene opening, in a composite insulator layer, is used to accommodate a subsequent dual damascene metal structure, comprised of an overlying, wide diameter, metal interconnect structure, and an underlying, narrow diameter, metal via structure. However to further decrease the diameter of the subsequent metal via structure, in an effort to increase device density, a novel spacer technology is employed. The use of insulator spacers, formed on the exposed sides of the dual damascene opening, result in a narrowing of the narrow diameter opening, thus allowing metal via structures to be realized, that are narrower in diameter than counterparts formed in openings achieved using only photolithographic patterning procedures. In addition this invention allows the photolithographic process window, for either critical dimension, or overlay, to be increased, thus avoiding possible image, or overlay problems, encountered with the use of more aggressive groundrules. The use of the spacers reduce the diameter of the openings, to a level only achievable using riskier photolithographic procedures. Prior art, such as Irinoda, in U.S. Pat. No. 5,726,499, describes a process in which spacers are used as part of an etch mask, to decrease the diameter of an etch mask opening, used to define an underlying, smaller diameter opening. In contrast, this invention does not use the spacer as an etch mask, but fabricates the spacer on the walls of a formed, small diameter opening, which was achieved using only conventional photolithographic and dry etching procedures, followed by the narrowing of the narrow diameter opening, via formation of the insulator spacer.